SI5376 Datasheet, PDF (59/66 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5376
Table 10. Si5376 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal
Level
Description
D1
CS_CA_A I/O LVCMOS DSPLLq Input Clock Select/Active Clock Indicator.
A6
CS_CA_B
Input: In manual clock selection mode, this pin functions as the
F9
CS_CA_C
manual input clock selector if the CKSEL_PIN is set to 1.
J4
CS_CA_D
0 = Select CKIN1
1 = Select CKIN2
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this
function and this input tristates. If configured for input, must be
tied high or low.
Output: In automatic clock selection mode, this pin indicates
which of the two input clocks is currently the active clock. If
alarms exist on both clocks, CK_ACTV will indicate the last active
clock that was used before entering the digital hold state. The
CK_ACTV_PIN register bit must be set to 1 to reflect the active
clock status to the CK_ACTV output pin.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status
will always be reflected in the CK_ACTV_REG read only register
bit.
G5
SCL
I LVCMOS _I²_{C Serial Clock.}
This pin functions as the serial clock input.
This pin has a weak pull-down.
G6
SDA
I/O LVCMOS _I²_{C Serial Data.}
I²C pin functions as the bi-directional serial data port.
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5376 Register Map.
Rev. 1.0
59