SI5376 Datasheet, PDF (16/66 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5376
5. Si5376 Application Examples and Suggestions
5.1. Schematic and PCB Layout
For a typical application schematic and PCB layout, see the Si537x-EVB Evaluation Board User's Guide, which
can be downloaded from www.silabs.com/timing.
In order to preserve the ultra low jitter of the Si5376 in applications where the four different DSPLL's are each
operating at different frequency, special care and attention must be paid to the PCB layout. The following is a list of
rules that should be observed:
1. The four Vdd supplies should be isolated from one another with four ferrite beads. They should be
separately bypassed with capacitors that are located very close to the Si5376 device.
2. Use a solid and undisturbed ground plane for the Si5376 and all of the clock input and output return paths.
3. For applications that wish to logically connect the four RESET signals, do not tie them together underneath
the BGA package. Instead connect them outside of the BGA footprint.
4. As much as is possible, do not route clock input and output signals underneath the BGA package. The
clock output signals should go directly outwards from the BGA footprint.
5. Avoid placing the OSC_P and OSC_N signals on the same layer as the clock outputs. Add grounded guard
traces surrounding the OSC_P and OSC_N signals.
6. Where possible, place the CKOUT and CKIN signals on separate PCB layers with a ground layer between
them. The use of ground guard traces between all clock inputs and outputs is recommended.
For more information, see the Si537x-EVB Evaluation Board User's Guide and Appendix I of the Si53xx Reference
Manual, Rev 0.5 or higher.
5.2. Thermal Considerations
The Si5376 dissipates a significant amount of heat and it is important to take this into consideration when designing
the Si5376 operating environment. Among other issues, high die temperatures can result in increased jitter and
decreased long term reliability. It is therefore recommended that one or more of the following occur:
1. Use a heat sink—A heat sink example is Aavid part number 375324B00035G.
2. Use a Vdd voltage of 1.8 V.
3. Limit the ambient temperature to significantly less that 85 °C.
4. Implement very good air flow.
5.3. SCL Leakage
When selecting pull up resistors for the two I²C signals, note that there is an internal pull down resistor of 18 k
from the SCL pin to ground. This comment does not apply to the SDA pin.
5.4. RSTL_x Pins
It is recommended that the four RSTL_x pins (RSTL_A, RSTL_B, RSTL_C and RSTL_D) be logically connected
together such that all four DSPLLs are either in or out of reset mode. When a DSPLL is in reset mode, its VCO will
not be locked to any signal and may drift across its operating range. If a drifting VCO has a frequency similar to that
of an operating VCO, there could be some crosstalk between the two VCOs. To avoid this from occurring during
device initialization, DSPLLsim loads each DSPLL with default Free Run frequency plans with VCO values apart
from one another. If the four RSTL_x pins are directly connected to one another, the connections should not be
made directly underneath the BGA package. Instead, the connections should be made outside the package
footprint.
16
Rev. 1.0