SI5376 Datasheet, PDF (11/66 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5376
Table 5. Performance Specifications
V_DD = 1.8 V ±5% or 2.5 V ±10%, T_A = –40 to 85 °C
Parameter
Symbol
Test Condition
PLL Performance*
Lock Time
Output Clock Phase Change
Closed Loop Jitter Peaking
Jitter Tolerance
Phase Noise
fout = 622.08 MHz
Spurious Noise
Jitter Generation
t_LOCKMP
t_{P_STEP}
J_PK
J_TOL
CKO_PN
SP_SPUR
J_GEN
Start of ICAL to of LOL,
FASTLOCK disabled
After clock switch
f3  128 kHz
Jitter Frequency Loop
Bandwidth
1 kHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
Max spur @ n x F3
(n  1, n x F3 < 100 MHz)
f_IN = f_OUT = 622.08 MHz,
BW = 120 Hz
LVPECL output
12 kHz–20 MHz
50 kHz–80 MHz
*Note: fin = fout = 622.08 MHz; BW = 120 Hz; LVDS.
Min
Typ
—
35
—
200
—
0.05
5000/BW —
—
–106
—
–114
—
–116
—
–132
—
–70
—
350
—
410
Max Unit
1200 ms
—
ps
0.1
dB
—
ns
pk-pk
— dBc/Hz
— dBc/Hz
— dBc/Hz
— dBc/Hz
—
dBc
410 fs rms
— fs rms
Rev. 1.0
11