SI5376 Datasheet, PDF (58/66 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5376
Pin #
B2
A3
B3
E4
C8
A8
B8
C9
H7
J7
H8
H9
G1
H2
J2
G2
C2
D2
C3
D3
Table 10. Si5376 Pin Descriptions (Continued)
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CKIN1P_A
CKIN1N_A
CKIN2P_A
CKIN2N_A
I/O
GND
I
Signal
Level
Supply
Description
Ground for each DSPLLq.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. See
recommended layout.
Multi
Clock Inputs for DSPLLq.
Differential input clocks. This input can also be driven with a sin-
gle-ended signal.
B7
CKIN1P_B
B6
CKIN1N_B
C7
CKIN2P_B
C6
CKIN2N_B
G8
CKIN1P_C
F8
CKIN1N_C
G7
CKIN2P_C
F7
CKIN2N_C
H3
CKIN1P_D
H4
CKIN1N_D
G3
CKIN2P_D
G4
CKIN2N_D
E2
LOL_A
O LVCMOS DSPLLq Loss of Lock Indicator.
C5
LOL_B
These pins function as the active high PLL loss of lock indicator if
E8
LOL_C
the LOL_PIN register bit is set to 1.
H5
LOL_D
0 = PLL locked.
1 = PLL unlocked.
If LOL_PINn = 0, this pin will tri-state. Active polarity is controlled
by the LOL_POLn bit. The PLL lock status will always be
reflected in the LOL_INTn read only register bit.
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5376 Register Map.
58
Rev. 1.0