SI53320 Datasheet, PDF (6/25 Pages) Silicon Laboratories – 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53320
Table 7. Additive Jitter, Single-Ended Clock Input
V_DD
Input^1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)³
Freq Clock Format Amplitude SE 20%-80% Clock Format
Typ
Max
(MHz)
V_IN
(single-ended,
Slew Rate
(V/ns)
peak to peak)
3.3 156.25 Single-ended
2.18
1
LVPECL
160
185
2.5 156.25 Single-ended
2.18
1
LVPECL
145
185
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. DC-coupled single-ended inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
CLK SYNTH
SMA103A
PSPL 5310A
Balun
CLKx
Si533xx
50
DUT
50
/CLKx
PSPL 5310A
Balun
AG E5052 Phase Noise
Analyzer
50ohm
Figure 1. Differential Measurement Method Using a Balun
Table 8. Thermal Conditions
Parameter
Thermal Resistance,
Junction to Ambient
Symbol
_JA
Test Condition
Still air
Value
93.88
Unit
°C/W
6
Rev. 1.0