SI53320 Datasheet, PDF (18/25 Pages) Silicon Laboratories – 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53320
3. Pin Description: 20-Pin TSSOP
Q0 1
Q0 2
Q1 3
Q1 4
Q2 5
Q2 ⁶
Q3 7
Q3 8
Q4 9
Q4 10
20 VDD
19 _OE
18 VDD
17 CLK1
16 CLK1
15 NC
14 CLK0
13 CLK0
12 CLK_SEL
11 GND
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
Name
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
GND
CLK_SEL
13
CLK0
Table 13. Si53320 20-Pin TSSOP Descriptions*
Type*
O Output clock 0.
Description
O Output clock 0 (complement).
O Output clock 1.
O Output clock 1 (complement).
O Output clock 2.
O Output clock 2 (complement).
O Output clock 3.
O Output clock 3 (complement).
O Output clock 4.
O Output clock 4 (complement).
GND Ground.
I
Mux input select pin (LVCMOS).
When CLK_SEL is high, CLK1 is selected.
When CLK_SEL is low, CLK0 is selected.
CLK_SEL contains an internal pull-down resistor.
I
Input clock 0.
18
Rev. 1.0