SI53320 Datasheet, PDF (10/25 Pages) Silicon Laboratories – 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53320
2.2. Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.
The non-inverting input is biased with a 18.75 k pull-down to GND and a 75 k pull-up to V_DD. The inverting input
is biased with a 75 k pull-up to V_DD.
V_DD
R_PU
R_PU
+
R_PD
–
R_PU = 75 k
R_PD = 18.75 k
CLK0 or
CLK1
Figure 5. Input Bias Resistors
2.3. Glitchless Clock Input Switching
The Si53320 features glitchless switching between two valid input clocks. Figure 6 illustrates that switching
between input clocks does not generate runt pulses or glitches at the output.
CLK1
CLK0
CLK_SEL
Note 1
Note 2
Note 3
Qn
Notes:
1. Q_n continues with CLK0 for 2-3 falling edges of CLK0.
2. Q_n is disabled low for 2-3 falling edges of CLK1 .
3. Q_n starts on the first rising edge after 1 + 2.
Figure 6. Glitchless Input Clock Switch
The Si53320 supports glitchless switching between clocks at the same frequency. In addition, the device supports
glitchless switching between 2 input clocks that are up to 10x different in frequency. When a switchover to a new
clock is made, the output will disable low after two or three clock cycles of the previously-selected input clock. The
outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start
from the newly-selected input. In the case a switchover to an absent clock is made, the output will glitchlessly stop
low and wait for edges of the newly selected clock. A switchover from an absent clock to a live clock will also be
glitchless. Note that the CLK_SEL input should not be toggled faster than 1/250th the frequency of the slower input
clock.
10
Rev. 1.0