SI53320 Datasheet, PDF (1/25 Pages) Silicon Laboratories – 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53320
1:5 LOW JITTER LVPECL CLOCK BUFFER
WITH 2:1 INPUT MUX
Features
 5 LVPECL outputs
 20-TSSOP
 Ultra-low additive jitter: 100 fs rms  RoHS compliant, Pb-free
 Wide frequency range: 1 to 725 MHz  Industrial temperature range:
 Input compatible with LVPECL,
–40 to +85 °C
LVDS, CML, HCSL, LVCMOS
 Footprint-compatible with
 2:1 mux
MC100LVEP14, SY100EP14U
 Glitchless input clock switching
 Synchronous output enable
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Description
The Si53320 is an ultra low jitter five output LVPECL buffer with synchronous OE.
Outputs are enabled/disabled in a low state, ensuring runt pulses are not created
when the device is enabled/disabled. The Si53320 features a 2:1 input mux,
making it ideal for redundant clocking applications. The Si53320 utilizes Silicon
Laboratories’ advanced CMOS technology to fanout clocks from 1 to 725 MHz
with guaranteed low additive jitter, low skew, and low propagation delay variability.
The Si53320 features minimal cross-talk and provides superior supply noise
rejection, simplifying low jitter clock distribution in noisy environments.
Functional Block Diagram
Ordering Information:
See page 20.
Pin Assignments
Q0 1
Q0 2
Q1 3
Q1 4
Q2 5
Q2 ⁶
Q3 7
Q3 8
20 VDD
19 _OE
18 VDD
17 CLK1
16 CLK1
15 NC
14 CLK0
13 CLK0
VDD
Power
Supply
Filtering
Q4 9
Q4 10
12 CLK_SEL
11 GND
Q0
CLK0
0
CLK0
Q0
Q1
Patents pending
Q1
Q2
Q2
CLK1
1
Q3
CLK1
Q3
Q4
CLK_SEL
Switching
Logic
Q4
GND
OE
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si53320