SI53320 Datasheet, PDF (19/25 Pages) Silicon Laboratories – 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53320
Table 13. Si53320 20-Pin TSSOP Descriptions* (Continued)
Pin #
14
Name
CLK0
15
NC
Type*
I
—
Description
Input clock 0 (complement)
When CLK0 is driven by a single-ended input, connect CLK0 to an appropriate
bias voltage (e.g., for a CMOS input apply V_DD/2).
No connect. Leave this pin unconnected.
16
CLK1
I
Input clock 1.
17
CLK1
18
V_DD
19
OE
I
Input clock 1 (complement)
When CLK1 is driven by a single-ended input, connect CLK1 to an appropriate
bias voltage (e.g., for a CMOS input apply V_DD/2).
P Core voltage supply.
Bypass with 1.0 µF capacitor and place as close to the V_DD pin as possible.
I
Output enable.
When OE = low, the clock outputs are enabled.
When OE = high, Q is held low and Q is held high.
OE features an internal pull-down resistor and may be left unconnected.
20
V_DD
P Core voltage supply.
Bypass with 1.0 µF capacitor and place as close to the V_DD pin as possible.
*Note: Pin types are: I = input, O = output, P = power, GND = ground.
Rev. 1.0
19