SI53320 Datasheet, PDF (11/25 Pages) Silicon Laboratories – 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53320
2.4. Synchronous Output Enable
The Si53320 features a synchronous output enable (disable) feature. The output enable pin is sampled and
synchronized to the falling edge of the input clock. This feature prevents runt pulses from being generated when
the outputs are enabled or disabled.
When OE is high, Q is held low and Q is held high. The device features an internal pull-down resistor, so the
outputs are enabled when the output enable pin is unconnected. See Table 5, “AC Characteristics,” on page 4 for
output enable and output disable times.
2.5. Input Mux and Output Enable Logic
The Si53320 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings.
Table 12. Input Mux and Output Enable Logic
CLK_SEL CLK0
CLK1
OE¹
Q²
L
L
X
L
L
L
H
X
L
H
H
X
L
L
L
H
X
H
L
H
X
X
X
H
L³
Notes:
1. Output enable active low
2. On the next negative transition of CLK0 or CLK1.
3. Q=low, Q=high
Rev. 1.0
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