SI53320 Datasheet, PDF (4/25 Pages) Silicon Laboratories – 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53320
Table 4. Output Characteristics (LVPECL)
(V_DD = 2.5 V ± 5%, or 3.3 V ± 10%,T_A = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Output DC Common Mode
Voltage
V_COM
V_DD – 1.595
Single-Ended
V_SE
0.55
Output Swing*
*Note: Unused outputs can be left floating. Do not short unused outputs to ground.
Typ
—
0.80
Max
V_DD – 1.245
Unit
V
1.050
V
Table 5. AC Characteristics
(V_DD = 2.5 V ± 5%, or 3.3 V ± 10%,T_A = –40 to 85 °C)
Parameter
Frequency
Symbol
F
Test Condition
LVPECL
Min Typ Max Unit
1
—
725 MHz
Duty Cycle
(50% input duty cycle)
Minimum Input Clock
Slew Rate
D_C
20/80% T_R/T_F<10% of period
48
50
52
%
(Differential)
SR
Required to meet prop delay and 0.75
—
additive jitter specifications
(20–80%)
—
V/ns
Output Rise/Fall Time
T_R/T_F
20/80%
—
—
350
ps
Minimum Input Pulse
Width
Propagation Delay
Output Enable Time
T_W
T_PLH,
T_PHL
T_EN
Output Disable Time
T_DIS
Output to Output Skew¹
T_SK
F = 1 MHz
F = 100 MHz
F = 725 MHz
F = 1 MHz
F = 100 MHz
F = 725 MHz
500
—
—
ps
700
950 1200
ps
—
1500
—
ns
—
30
—
ns
—
10
—
ns
—
2000
—
ns
—
30
—
ns
—
10
—
ns
—
60
90
ps
Part to Part Skew²
T_PS
Differential
—
—
150
ps
Notes:
1. Output-to-output skew specified for outputs with identical configuration.
2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DD (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
4
Rev. 1.0