SI53320 Datasheet, PDF (5/25 Pages) Silicon Laboratories – 1:5 LOW JITTER LVPECL CLOCK BUFFER

Si53320
Table 5. AC Characteristics (Continued)
(V_DD = 2.5 V ± 5%, or 3.3 V ± 10%,T_A = –40 to 85 °C)
Parameter
Power Supply Noise
Rejection³
Symbol
PSRR
Test Condition
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
Min Typ Max Unit
—
–67.5
—
dBc
—
–62.5
—
dBc
—
–60
—
dBc
1 MHz sinusoidal noise
—
–55
—
dBc
Notes:
1. Output-to-output skew specified for outputs with identical configuration.
2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DD (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
Table 6. Additive Jitter, Differential Clock Input
V_DD
Input^1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)³
Freq Clock Format Amplitude
Differential Clock Format
Typ
Max
(MHz)
V_IN
20%-80% Slew
(Single-Ended, ^{Rate (V/ns)}
Peak-to-Peak)
3.3
725
Differential
0.15
0.637
LVPECL
45
65
3.3 156.25 Differential
0.5
0.458
LVPECL
160
185
2.5
725
Differential
0.15
0.637
LVPECL
45
65
2.5 156.25 Differential
0.5
0.458
LVPECL
145
185
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
Rev. 1.0
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