SI53320 Datasheet, PDF (21/25 Pages) Silicon Laboratories – 1:5 LOW JITTER LVPECL CLOCK BUFFER

5. Package Outline
5.1. 20-TSSOP Package Diagram
Si53320
Figure 13. Si53320 20-TSSOP Package Diagram
Table 14. Package Dimensions
Dimension
A
A1
A2
Min
—
0.05
0.80
Nom
Max
—
1.20
—
0.15
1.00
1.05
Dimension
Min
e
L
0.45
L2
Nom
0.65 BSC
0.60
0.25 BSC
Max
0.75
b
0.19
—
0.30

0
—
8
c
0.09
—
0.20
aaa
0.10
D
6.40
6.50
6.60
bbb
0.10
E
6.40 BSC
ccc
0.20
E1
4.30
4.40
4.50
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.0
21