SI53108 Datasheet, PDF (6/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
Table 5. Output Relational Timing Parameters
T_A = –40 to 85 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Test Condition
Min TYP Max Unit Notes
CLK_IN, DIF[x:0] Input-to-Output Delay in PLL Mode
Nominal Value
–100
20
100
ps 1,2,4,5
CLK_IN, DIF[x:0] Input-to-Output Delay in Bypass Mode
Nominal Value
2.5
3.3
4.5
ns
2,3,5
CLK_IN, DIF[x:0] Input-to-Output Delay Variation in PLL
–100
39
100
ps
2,3,5
mode (over voltage and temperature)
Nominal Value
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in Bypass
Mode (over voltage and temperature)
Nominal Value
–250
250
ps
2,3,5
CLK_IN, DIF[7:0] Output-to-Output Skew across all 12 out- 0
puts (Common to Bypass and PLL mode)
25
50
ps 1,2,3,5
Notes:
1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2. Measured from differential cross-point to differential cross-point.
3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created
by it.
4. This parameter is deterministic for a given device.
5. Measured with scope averaging on to find mean value
Table 6. PLL Bandwidth and Peaking
T_A = –40 to 85 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Test Condition
HBW_BYPASS_LBW = 0
HBW_BYPASS_LBW = 1
HBW_BYPASS_LBW = 1
HBW_BYPASS_LBW = 0
Min TYP Max Unit Notes
—
0.4
2.0
dB
2
—
0.1
2.0
dB
2
2
3
4
MHz
1
0.7
1
1.4 MHz
1
Notes:
1. Measured at 3 db down or half power point.
2. Measured as maximum pass band gain. At frequencies with the loop BW, highest point of magnification is call PLL
jitter peaking.
6
Rev. 1.2