SI53108 Datasheet, PDF (5/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
Table 3. Clock Input Parameters
T_A = –40 to 85 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Input Frequency
Symbol
F_IN
Input High Voltage- CLK_IN V_IHDIF
Input Low Voltage- CLK_IN V_ILDIF
Input Common Mode
Voltage - CLK_IN
Input Amplitude- CLK_IN
Input Slew Rate- CLK_IN
Input Leakage Current
Input Duty Cycle
V_COM
V_Swing
IDD_VDDAPD
I_IN
d_tin
Input Jitter, Cycle-Cycle
Input SS Modulation Fre-
quency
J_DIFIN
f_MODIN
Test Condition
Bypass Mode
PLL Mode, 100 MHz
PLL Mode, 133.33 MHz
Differential inputs
single-ended measurement
Differential inputs
single-ended measurement
Common Mode Voltage Input
Peak to Peak
Measured differentially
V_IN = V_DD, V_IN = GND
Measured from differential
waveform
Differential measurement
Triangle Wave Modulation
Min
Typ Max
33
—
150
90
100 110
120 133.33 147
600
800 1150
V_SS –300
0
300
—
300
1000
300
— 1450
0.4
—
8
–5
—
5
45
—
55
0
—
125
30
—
33
Unit
MHz
MHz
MHz
mV
mV
mV
V/ns
A
%
ps
kHz
Table 4. Current Consumption
T_A = –40 to 85 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Min Typ Max Unit
Operating Current IDD_VDD
133 MHz, VDD Rail
—
IDD_VDDA
133 MHz, VDDA + VDDR, PLL Mode —
Power Down Current IDD_VDDPD Power Down, VDD Rail
—
IDD_VDDAPD Power Down, VDDA Rail
—
79
90
mA
14
20
mA
1
1.5
mA
4
8
mA
Rev. 1.2
5