SI53108 Datasheet, PDF (30/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Table 27. Si53108 48-Pin QFN Descriptions
Name
PWRGD/PWRDN
GND
VDDR
CLK_IN
CLK_IN
SDA
SCL
FB_OUT_NC
FB_OUT_NC
VDD
OE_0
NC
DIF_0
DIF_0
VDD
DIF_1
DIF_1
OE_1
VDD
NC
DIF_2
DIF_2
OE_2
OE_3
DIF_3
DIF_3
Type
Description
I 3.3 V LVTTL input to power up or power down the device.
GND Connect this pin to ground.
VDD 3.3 V power supply for differential input receiver. This VDDR should be
treated as an analog power rail and filtered appropriately.
I, DIF 0.7 V Differential input.
I, DIF 0.7 V Differential input.
I/O Open collector SMBus data.
I/O SMBus slave clock input.
I/O No connect. There are active signals on pin 8 and 9, do not connect
anything to these pins.
I/O No connect. There are active signals on pin 8and 9, do not connect
anything to these pins.
3.3 V 3.3 V power supply
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
- Do not connect this pin to anything.
O, DIF 0.7 V Differential clock output. Default is 1:1.
O, DIF 0.7 V Differential clock output. Default is 1:1.
3.3 V 3.3 V power supply for outputs.
O, DIF 0.7 V Differential clock output. Default is 1:1.
O, DIF 0.7 V Differential clock output. Default is 1:1.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
3.3 V 3.3 V power supply
- Do not connect this pin to anything.
O, DIF 0.7 V Differential clock output. Default is 1:1.
O, DIF 0.7 V Differential clock output. Default is 1:1.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
O, DIF 0.7 V Differential clock output. Default is 1:1.
O, DIF 0.7 V Differential clock output. Default is 1:1.
30
Rev. 1.2