SI53108 Datasheet, PDF (21/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
4. Control Registers
4.1. Byte Read/Write
Reading or writing a register in an SMBus slave device in byte mode always involves specifying the register
number.
4.1.1. Byte Read
The standard byte read is as shown in Figure 7. It is an extension of the byte write. The write start condition is
repeated; then, the slave device starts sending data, and the master acknowledges it until the last byte is sent. The
master terminates the transfer with a NAK, then a stop condition. For byte operation, the 2 x 7th bit of the
command byte must be set. For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte
must be the byte transfer count.
1
7
T Slave
11
8
Wr A _Command
11
7
A ^r Slave
11
8
11
Rd A Data Byte 0 _{N P}
Command
starT
Condition
Register # to
read
2 x 7 bit = 1
Byte Read Protocol
repeat starT
Acknowledge
Not ack
Master to
stoP
Condition
Slave to
Figure 7. Byte Read Protocol
4.1.2. Byte Write
Figure 8 illustrates a simple, typical byte write. For byte operation, the 2 x 7th bit of the command byte must be set.
For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte must be the byte transfer count.
The count can be between 1 and 32. It is not allowed to be zero or to exceed 32.
1
7
T Slave
11
8
Wr A _Command
1
8
11
A Data Byte 0 ^A P
Command
starT Condition
Register # to
write
2 x 7 bit = 1
Byte Write Protocol
Acknowledge ^{stoP Condition}
Master to
Slave to
Figure 8. Byte Write Protocol
Rev. 1.2
21