SI53108 Datasheet, PDF (10/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
Table 8. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode) (Continued)
Parameter
Symbol
CLK 100 MHz, 133 MHz
Unit
Notes
Min
Typ
Max
Ringback Voltage
V_rb
0.2
N/A
V
4,7
Notes:
1. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of
CLK#
2. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from -150 mV
to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making most of the
dynamic wiggles along the clock edge Only valid for Rising clock and Falling Clock#. Signal must be monotonic through
the V_OL to V_OH region for T_RISE and T_FALL.
3. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing
4. Test configuration is R_S = 33.2 Ω, R_P = 49.9, 2 pF for 100 Ω transmission line; R_S = 27 Ω, R_P = 42.2, 2 pF for 85 Ω
transmission line
5. The average period over any 1 μs period of time must be greater than the minimum and less than the maximum
specified period
6. V_CROSS(rel) Min and Max are derived using the following, V_CROSS(rel) Min = 0.250 + 0.5 (V_HAVG - 0.700), V_CROSS(rel)
Max = 0.550 - 0.5 (0.700 – V_HAVG) (see Figure 3-4 for further clarification)
7. Measurement taken from Single Ended waveform
8. Measurement taken from differential waveform
9. Unless otherwise noted, all specifications in this table apply to all processor frequencies
10. V_HIGH is defined as the statistical average High value as obtained by using the Oscilloscope V_HIGH Math function
11. V_LOW is defined as the statistical average Low value as obtained by using the Oscilloscope V_LOW Math function
12. Overshoot is defined as the absolute value of the maximum voltage
13. Undershoot is defined as the absolute value of the minimum voltage
14. The crossing point must meet the absolute and relative crossing point specifications simultaneously
15. ∆V_CROSS is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK#. This is the
maximum allowed variance in V_CROSS for any particular system
16. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are
100,000,000 Hz, 133,333,333 Hz
17. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are
99,750,00 Hz, 133,000,000 Hz
18. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
19. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the
falling edge rate (average) of clock#
20. Measured with device in PLL mode, in BYPASS mode jitter is additive (up to 25ps of cycle-to-cycle jitter may add to the
input jitter)
21. Rise/Fall matching is derived using the following, 2 * (T_RISE –T_FALL) / (T_RISE +T_FALL)
22. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8 V – 2.0 V to the
time that stable clocks are output from the buffer chip (PLL locked)
10
Rev. 1.2