SI53108 Datasheet, PDF (13/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
Table 10. Clock Periods Differential Clock Outputs with SSC Disabled
SSC ON
Measurement Window
Unit
Center
Freq, MHz ^{1 Clock}
1 µs
0.1 s
0.1 s
0.1 s
1 µs
1 Clock
–C–C
Jitter
AbsPer
Min
–SSC
Short
Term AVG
Min
–ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
+C-C
Jitter
AbsPer
Max
100.00 9.94900
9.99900 10.00000 10.00100
10.05100
ns
133.33 7.44925
7.49925 7.50000 7.50075
7.55075
ns
Table 11. Clock Periods Differential Clock Outputs with SSC Enabled
SSC ON
Measurement Window
Unit
Center
Freq, MHz ^{1 Clock}
1 µs
0.1 s
0.1 s
0.1 s
1 µs
1 Clock
–C–C
Jitter
AbsPer
Min
–SSC
Short
Term AVG
Min
–ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
+C-C
Jitter
AbsPer
Max
99.75
9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126
ns
133.33 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845
ns
Rev. 1.2
13