SI53108 Datasheet, PDF (11/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
Table 9. DIF 0.7 V AC Timing Characteristics (–0.5% Spread Spectrum Mode)
Parameter
Symbol
CLK 100 MHz, 133 MHz
Min
Clock Stabilization Time
T_STAB
Long Term Accuracy
L_ACC
Absolute Host CLK Period (100 MHz) T_ABS
Absolute Host CLK Period (133 MHz) T_ABS
Edge _rate
Edge _rate
—
—
9.94900
7.44925
1.0
Typ
Max
1.8
100
10.10126
7.58845
4.0
Rise/Fall Matching
Voltage High (typ 0.70 V)
Voltage Low (typ 0.0 V)
Maximum Voltage
Absolute Crossing Point Voltages
T_{RISE_MAT}/
T_{FALL_MAT}
V_HIGH
V_LOW
V_MAX
V_CROSS(a
bs)
—
660
–150
—
300
20
850
150
1150
550
Relative Crossing Point Voltages
V_CROSS(re
l)
Calc
Calc
Total Variation of V_cross Over All
Total ∆
—
140
Edges
V_CROSS
Cycle-to-Cycle Jitter
T_CCJITTER
50
Duty Cycle
Duty Cycle
45
55
Maximum Voltage (Overshoot)
Maximum Voltage (Undershoot)
V_ovs
—
V_uds
—
V_High + 0.3
V_Low – 0.3
Unit
ms
ppm
ns
ns
V/ns
%
mV
mV
mV
mV
mV
mV
ps
%
V
V
Notes
22
4,8,16
4,5,8
4,5,8
2,4,8
4,7,19,21
4,7,10
4,7,11
7
1,3,4,7,14
4,6,7,14
4,7,15
4,8,20
4,8
4,7,12
4,7,13
Rev. 1.2
11