SI53108 Datasheet, PDF (31/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
Table 27. Si53108 48-Pin QFN Descriptions
Pin #
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Name
Type
Description
VDD
3.3 V 3.3 V power supply
DIF_4
O, DIF 0.7 V Differential clock output. Default is 1:1.
DIF_4
O, DIF 0.7 V Differential clock output. Default is 1:1.
OE_4
OE_5
DIF_5
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
O, DIF 0.7 V Differential clock output. Default is 1:1.
DIF_5
O, DIF 0.7 V Differential clock output. Default is 1:1.
VDD
3.3 V 3.3 V power supply
DIF_6
O, DIF 0.7 V Differential clock output. Default is 1:1.
DIF_6
O, DIF 0.7 V Differential clock output. Default is 1:1.
OE_6
VDD
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
3.3 V 3.3 V power supply
DIF_7
O, DIF 0.7 V Differential clock output. Default is 1:1.
DIF_7
O, DIF 0.7 V Differential clock output. Default is 1:1.
OE_7
VDD
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
3.3 V 3.3 V power supply
NC
- Do not connect this pin to anything.
VDDA
3.3V 3.3 V power supply for PLL.
NC
- Do not connect this pin to anything.
NC
- Do not connect this pin to anything.
100M_133M
HBW_BYPASS_LBW
GND
I,SE 3.3 V tolerant inputs for input/output frequency selection. An external pull-
up or pull-down resistor is attached to this pin to select the input/output
frequency.
High = 100 MHz output
Low = 133 MHz output
I, SE
Tri-Level input for selecting the PLL bandwidth or bypass mode.
High = High BW mode
Med = Bypass mode
Low = Low BW mode
GND Ground epad to GND.
Rev. 1.2
31