SI53108 Datasheet, PDF (18/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
a good design practice to include the filters.
PWRDN: If a clock buffer is placed in PWRDN mode, the SDATA and SCLK inputs must be Tri-stated and the
device must retain all programming information. IDD current due to the SMBus circuitry must be characterized and
in the data sheet.
18
Rev. 1.2