SI53108 Datasheet, PDF (4/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
1. Electrical Specifications
Table 1. Absolute Maximum Ratings
Parameter
3.3 V Core Supply Voltage¹
3.3 V I/O Supply Voltage¹
3.3 V Input High Voltage^1,2
3.3 V Input Low Voltage¹
Storage Temperature¹
Input ESD protection³
Symbol
V_DD/V_{DD_A}
V_{DD_IO}
V_IH
V_IL
t_s
ESD
Min
—
—
—
−0.5
–65
2000
Max
4.6
4.6
4.6
—
150
—
Notes:
1. Consult manufacturer regarding extended operation in excess of normal DC operating parameters.
2. Maximum V_IH is not to exceed maximum V_DD.
3. Human body model.
Unit
V
V
V
V
°C
V
Table 2. DC Operating Characteristics
V_{DD_A} = 3.3 V±5%, V_DD = 3.3 V±5%
Parameter
Symbol
Test Condition
Min
Max
Unit
3.3 V Core Supply Voltage
VDD/VDD_A
3.3 V ±5%
3.135
3.465
V
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input Leakage Current¹
3.3 V Input High Voltage²
3.3 V Input Low Voltage²
3.3 V Input Low Voltage
3.3 V Input Med Voltage
3.3 V Input High Voltage
3.3 V Output High Voltage³
3.3 V Output Low Voltage³
Input Capacitance⁴
DIFF_IN Capacitance
Output pin Capacitance
Output Capacitance⁴
Pin Inductance
Ambient Temperature
V_IH
V_IL
I_IL
V_{IH_FS}
V_{IL_FS}
V_{IL_Tri}
V_{IM_Tri}
V_{IH_Tri}
V_OH
V_OL
C_IN
C_{DIF_IN}
C_OUT
C_OUT
L_PIN
T_A
VDD
0 < VIN < VDD
VDD
I_OH = –1 mA
I_OL = 1 mA
No Airflow
2.0
VDD+0.3 V
VSS-0.3
0.8
V
–5
+5
µA
0.7
VDD+0.3 V
VSS–0.3 0.35
V
0
0.8
V
1.2
1.8
V
2.2
VDD
V
2.4
—
V
—
0.4
V
2.5
4.5
pF
1.5
2.7
pF
6
pF
2.5
4.5
pF
—
7
nH
–40
85
°C
Notes:
1. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state
current requirements.
2. Internal voltage reference is to be used to guarantee V_IH_FS and V_IL_FS thresholds levels over full operating range.
3. Signal edge is required to be monotonic when transitioning through this region.
4. Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance.
4
Rev. 1.2