SI53108 Datasheet, PDF (33/38 Pages) Silicon Laboratories – DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Si53108
8. Package Outline
Figure 12 illustrates the package details for the Si53108. Table 28 lists the values for the dimensions shown in the
illustration.
Figure 12. 48-Pin Quad Flat No Lead (QFN) Package
Table 28. Package Diagram Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.15
0.20
0.25
D
6.00 BSC.
D2
3.50
3.60
3.70
e
0.40 BSC.
E
6.00 BSC.
E2
3.50
3.60
3.70
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.2
33