SI53019-A02A Datasheet, PDF (4/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN3 AND QPI BUFFER

Si53019-A02A
1. Electrical Specifications
Table 1. DC Operating Characteristics¹
V_{DD_A} = 3.3 V ±5%, V_DD = 3.3 V ±5%
Parameter
Symbol
Condition
Min
Max
Unit
3.3 V Core Supply Voltage
VDD/VDD_A
3.3 V ±5%
3.135
3.465
V
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input Leakage Current²
3.3 V Input High Voltage³
3.3 V Input Low Voltage³
3.3 V Input Low Voltage
3.3 V Input Med Voltage
3.3 V Input High Voltage
3.3 V Output High Voltage⁴
3.3 V Output Low Voltage⁴
Input Capacitance⁵
Output Capacitance⁵
Pin Inductance
Ambient Temperature
V_IH
V_IL
I_IL
V_{IH_FS}
V_{IL_FS}
V_{IL_Tri}
V_{IM_Tri}
V_{IH_Tri}
V_OH
V_OL
C_IN
C_OUT
L_PIN
T_A
V_DD
0 < VIN < V_DD
V_DD
I_OH = –1 mA
I_OL = 1 mA
No Airflow
2.0
V_DD+0.3
V
VSS–0.3
0.8
V
–5
+5
µA
0.7
V_DD+0.3
V
VSS–0.3 0.35
V
0
0.9
V
1.3
1.8
V
2.4
V_DD
V
2.4
—
V
—
0.4
V
2.5
4.5
pF
2.5
4.5
pF
—
7
nH
0
70
°C
Notes:
1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.
2. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state
current requirements.
3. Internal voltage reference is to be used to guarantee V_IH_FS and V_IL_FS thresholds levels over full operating range.
4. Signal edge is required to be monotonic when transitioning through this region.
5. Ccomp capacitance based on pad metalization and silicon device capacitance. Not including pin capacitance.
4
Rev. 1.1