SI53019-A02A Datasheet, PDF (16/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN3 AND QPI BUFFER

Si53019-A02A
2.4. CKPWRGD/PWRDN
CKPWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to
indicating a power-down condition. CKPWRGD (assertion) is used by the Si53019-A02A to sample initial
configurations, such as frequency select condition and SA selections. After CKPWRGD has been asserted high for
the first time, the pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and
instruct the device to invoke power-saving mode. PWRDN is a completely asynchronous active low input. When
entering power-saving mode, PWRDN should be asserted low prior to shutting off the input clock or power to
ensure all clocks shut down in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior
to turning off the VCO. When PWRDN is deasserted high, all clocks will start and stop without any abnormal
behavior and will meet all AC and DC parameters.
Note: The assertion and deassertion of PWRDN is absolutely asynchronous.
Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended.
Operation in this mode may result in glitches, excessive frequency shifting, etc.
Table 18. CKPWRGD/PWRDN Functionality
CKPWRGD/ DIF_IN/
PWRDN DINF_IN#
0
X
1
Running
SMBus
EN bit
X
0
OE# Pin
X
X
DIF(5:12)
DIF(5:12)#
Hi-Z^*
Hi-Z^*
Other DIF/
DIF#
Hi-Z^*
Hi-Z^*
FBOUT_NC/
FBOUT_NC#
Hi-Z^*
PLL State
OFF
Running
ON
1
0
Running
Running
Running
ON
1
1
Hi-Z^*
Running
Running
ON
*Note: Due to external pull down resistors, Hi-Z results in Low/Low on the True/Complement outputs.
16
Rev. 1.1