SI53019-A02A Datasheet, PDF (17/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN3 AND QPI BUFFER

Si53019-A02A
2.4.1. PWRDN Assertion
When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held Tri-
state/Tri-state on the next DIF high-to-low transition. The device will put all outputs in high impedance mode, and
all outputs will be pulled low by the external terminating resistors.
PWRDWN
DIF
DIF
Figure 2. PWRDN Assertion
2.4.2. CKPWRGD Assertion
The power-up latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion
of the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs
stopped in a Tri-state/Tri-state condition resulting from power down must be driven high in less than 300 µs of
PWRDN deassertion to a voltage greater than 200 mV.
PWRGD
DIF
Tstable
<1.8 ms
DIF
Tdrive_Pwrdn#
<300 µs; > 200 mV
Figure 3. PWRDG Assertion (Pwrdown—Deassertion)
Rev. 1.1
17