SI53019-A02A Datasheet, PDF (20/37 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN3 AND QPI BUFFER

Si53019-A02A
Skew measurement
point
0.000 V
High Duty Cycle %
TPeriod
Low Duty Cycle %
Figure 6. Differential (CLOCK–CLOCK) Measurement Points (T_period, Duty Cycle, Jitter)
3.2. Termination of Differential Outputs
All differential outputs are to be tested into a 100  or 85  differential impedance transmission line. Source
terminated clocks have some inherent limitations as to the maximum trace length and frequencies that can be
supported. For CPU outputs, a maximum trace length of 10” and a maximum of 200 MHz are assumed. For SRC
clocks, a maximum trace length of 16” and maximum frequency of 100 MHz is assumed. For frequencies beyond
200 MHz, trace lengths must be restricted to avoid signal integrity problems.
Table 21. Differential Output Termination
Clock
DIFF Clocks—50  configuration
DIFF Clocks—43  configuration
IREF ( )
475
412
Board Trace Impedance
100
85
Rs
Rp
Unit
33+5%
50

27+5% 42.2 or 43.2 
3.2.1. Termination of Differential Current Mode HCSL Outputs
10 inches
R_S
Differential Zo
R_P
R_P
R_S
2pF
2pF
Figure 7. 0.7 V Configuration Test Load Board Termination
20
Rev. 1.1