S-77100 Datasheet, PDF (8/40 Pages) Seiko Instruments Inc – POWER SEQUENCER

POWER SEQUENCER
S-77100/77101 Series
Rev.1.0_01
 Operation
1. Sequence operation
1. 1 S-77100A (Reverse type), S-77100B (Forward type)
The S-77100 Series has enable outputs of 4 channels (the ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the
ENBL_D pin). The order of the off-sequence operation is different in reverse type and forward type.
1. 1. 1 Sequence operation outline
(1) On-sequence operation
After the ON pin changes from "L" to "H", the external capacitor (CDLY) charge operation is started, and the
discharge operation is performed when CDLY is fully charged. The period during which this is repeated n times
is the delay time (tDLY), and the ENBL_A pin changes to "H". Similarly, each time tDLY elapses, the ENBL_B pin,
the ENBL_C pin and the ENBL_D pin change to "H" in turn. The period from when the ON pin changes from
"L" to "H" to when the ENBL_D pin changes to "H" is called "on-sequence period".
(2) Off-sequence operation
After the ON pin changes from "H" to "L", CDLY charge operation is started, and the discharge operation is
performed when CDLY is fully charged. The period during which this is repeated n times is tDLY, and the
ENBL_D pin, the ENBL_C pin, the ENBL_B pin and the ENBL_A pin change to "L" in turn in S-77100A. The
ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin change to "L" in turn in S-77100B. The
period from when the ON pin changes from "H" to "L" to when the ENBL_A pin in S-77100A or the ENBL_D pin
in S-77100B changes to "L" is called "off-sequence period".
Do not change the ON pin during on-sequence period and off-sequence period in order to perform the sequence
operation normally.
The number of times of CDLY charge and discharge which determines tDLY can be selected from 2 times / 4 times
/ 8 times / 16 times as the option.
CDLY charge operation and discharge operation to generate tDLY are performed by the constant current circuit.
Refer to " Relation between Delay Time and External Capacitor" for the relation of CDLY and tDLY.
In addition, the period from when the ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin all
change to "H" to when the off-sequence operation starts is called "power-good period", and the period from
when the ENBL_A pin, the ENBL_B pin, the ENBL_C pin and the ENBL_D pin all change to "L" to when the
on-sequence operation starts is called "off period".
Refer to Figure 5 for the peripheral circuit connection example.
Timing charts are shown in Figure 6 and Figure 7 for S-77100A and S-77100B, respectively.
5 V AUX _DC-DC
IN
LDO
OUT
3.3 V
0.1 F
S-77100 Series
VDD
ENBL_A
ON
ENBL_B
ENBL_C
CDLY
ENBL_D
VSS
IN OUT
EN
DC-DC
LDO
IN OUT
EN
DC-DC
LDO
DC-DC
LDO
IN OUT
2.5 V
I/O
1.8 V _LOGIC
EN
DC-DC
LDO
IN OUT
1.5 V
MEMORY
1.1 V
CORE
EN
SoC
Remark The ENBL_x pin is CMOS output.
Figure 5 Peripheral Circuit Connection Example (S-77100A: Reverse type, S-77100B: Forward type)
Caution 1.
2.
The input should be performed after the power supply voltage applied to the S-77100 Series
becomes stable condition.
The above connection diagram does not guarantee successful operation. Perform thorough
evaluation using the actual application to set the constant.
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