S-77100 Datasheet, PDF (24/40 Pages) Seiko Instruments Inc – POWER SEQUENCER

POWER SEQUENCER
S-77100/77101 Series
 Relation between Delay Time and External Capacitor
The S-77100/77101 Series sets the delay time (tDLY) with an external capacitor (CDLY).
tDLY is generated by performing CDLY charge-discharge operation.
Rev.1.0_01
ON
ENBL_A
ENBL_B
ENBL_C
ENBL_D
CDLY
Off period
Power-good
period
VSS
tDLY_OFFSET
tDLY
tDLY
Figure 27
1. tDLY approximate calculation formula
tDLY is calculated by using the following approximate calculation formula.
When CDLY ≤ 1 nF
tDLY [ms] = (1.206 × CDLY [nF] + 0.023) × the number of times of charge and discharge
When CDLY > 1 nF
tDLY [ms] = (1.155 × CDLY [nF] − 0.023) × the number of times of charge and discharge
2. Offset delay time (tDLY_OFFSET) approximate calculation formula
As shown in Figure 27, the CDLY pin during off period or power-good period is discharged to the VSS level. For this
reason, there is an offset delay time (tDLY_OFFSET) immediately after the transition from off period to on-sequence
period or from power-good period to off-sequence period.
tDLY_OFFSET varies depending on the capacitance of CDLY. tDLY_OFFSET is calculated by using the following approximate
calculation formula.
When CDLY ≤ 1 nF
tDLY_OFFSET [ms] = 0.241 × CDLY [nF] − 0.024
When CDLY > 1 nF
tDLY_OFFSET [ms] = 0.299 × CDLY [nF] − 0.150
24