S-77100 Datasheet, PDF (14/40 Pages) Seiko Instruments Inc – POWER SEQUENCER

POWER SEQUENCER
S-77100/77101 Series
Rev.1.0_01
_______
2. 2 S-77101A (Reverse type, with OFF pin)
The enable output can be increased by connecting S-77101A in cascade. The peripheral circuit connection
example how two S-77101A devices are connected in cascade is shown in Figure 13. _{_______}
Connect the ENBL_C pin of S-77101A(1) and the ON pin of S-77101A(2), and the OFF pin of S-77101A(1)
and the ENBL_A pin of S-77101A(2).
Figure 14 shows the timing chart.
5 V AUX
DC-DC
LDO
IN OUT _{3.3 V}
S-77101A(1)
3.3 V
0.1 F
VDD
ON
ENBL_A
OFF
ENBL_B
CDLY
ENBL_C
VSS
IN OUT
EN
DC-DC
LDO
IN OUT
EN
DC-DC
LDO
2.5 V
DC-DC
LDO _{1.8 V}
IN OUT
EN
1.5 V
I/O(1)
I/O(2)
LOGIC
S-77101A(2)
3.3 V
0.1 F
VDD
ON
ENBL_A
OFF
ENBL_B
CDLY
ENBL_C
VSS
IN OUT
EN
DC-DC
LDO
IN OUT
EN
DC-DC
LDO
System
2.5 V
DC-DC
LDO _{1.8 V}
IN OUT
EN
1.5 V
I/O(1)
I/O(2)
LOGIC
Remark The ENBL_x pin is CMOS output.
_______
Figure 13 Peripheral Circuit Connection Example (S-77101A: Reverse Type, with OFF pin)
Caution 1.
2.
3.
The input should be performed after the power supply voltage applied to S-77101A becomes
stable condition.
The above connection diagram does not guarantee successful operation. Perform thorough
evaluation using the actual application to set the constant.
The external capacitors (CDLY) connected to the CDLY pin of S-77101A(1) and S-77101A(2)
cannot use the same capacitor.
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