S-77100 Datasheet, PDF (18/40 Pages) Seiko Instruments Inc – POWER SEQUENCER

POWER SEQUENCER
S-77100/77101 Series
Rev.1.0_01
3. 1. 2 Operation when low voltage is detected
(1) When low voltage is detected during power-good period
Since the ENBL_x pins all change to "L" when the power supply voltage (VDD) is equal to or lower than the low
voltage detection voltage (VUVLO), the off-sequence operation timing is not guaranteed. Thereafter, if the ON
pin is "H" when VDD exceeds VUVLO, the on-sequence operation is performed automatically. If the ON pin is "L"
when VDD exceeds VUVLO, the on-sequence operation is not performed. In order to perform the on-sequence
operation, set the ON pin to "H" again. The operation example is shown in Figure 18.
VDD
VUVLO
VSS _Power-good
period
ON
CDLY
ENBL_A
ENBL_B
ENBL_C
ENBL_D
On-sequence period
Power-good period
On-sequence period
Figure 18
(2) When low voltage is detected during on-sequence period and off-sequence period
Since the ENBL_x pins all change to "L" when VDD is equal to or lower than VUVLO during on-sequence period
or off-sequence period, the off-sequence operation timing is not guaranteed. In addition, CDLY charge operation
is stopped and the automatic discharge operation is started. The operation example is shown in Figure 19.
VDD
VUVLO
VSS
ON
CDLY
ENBL_A
ENBL_B
ENBL_C
ENBL_D
Original on-sequence period
VDD
VUVLO
VSS
Original off-sequence period
ON
CDLY
ENBL_A
ENBL_B
ENBL_C
ENBL_D
Figure 19
Remark Refer to "3. Automatic discharge time (tDCHG) approximate calculation formula" in " Relation
between Delay Time and External Capacitor" for the automatic discharge operation.
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