S-77100 Datasheet, PDF (25/40 Pages) Seiko Instruments Inc – POWER SEQUENCER

Rev.1.0_01
POWER SEQUENCER
S-77100/77101 Series
3. Automatic discharge time (tDCHG) approximate calculation formula
Automatic discharge operation is the operation that electrical charge remained in CDLY is discharged.
After the charge-discharge operation is completed, the automatic discharge operation is performed by the constant
current circuit.
Special operation
ON On-sequence period
CDLY
On-sequence period
Idle
period
VSS
tDCHG
Figure 28
The automatic discharge operation of the S-77100/77101 Series is performed in the following cases.
• When the ON pin changes during on-sequence period. (Refer to Figure 28.)
• When on-sequence period is completed.
• When the O_{__}N_{____}p_{_}in changes during off-sequence period. (The S-77100 Series only)
• When the OFF pin changes during off-sequence period. (The S-77101 Series only)
• When off-sequence period is completed.
• When VDD is equal to or lower than VUVLO during on-sequence period or off-sequence period.
tDCHG varies depending on the capacitance of CDLY and is calculated by using the following approximate calculation
formula.
tDCHG [ms] = 0.219 × CDLY [nF]
The period from when the S-77100/77101 Series starts the automatic discharge operation to when it starts the next
on-sequence operation or the off-sequence operation is called "idle period". The idle period should be equal to or
longer than tDCHG. The idle period is necessary in order to discharge the electrical charge in CDLY completely and
start the next on-sequence operation or off-sequence operation normally.
In addition, by setting power-good period and off period equal to or longer than tDCHG during the sequence operation,
the next off-sequence period and the on-sequence period will be the intended length.
Caution 1.
2.
The capacitor of 100 pF to 47 nF can be used as CDLY.
CDLY should be placed as close to the S-77100/77101 Series as possible since the CDLY pin
internal impedance is high and the pin is easily affected by external noise etc.
tDLY, tDLY_OFFSET and tDCHG may not match the calculation formula due to parasitic capacitance of
the CDLY pin or internal delay in the IC. Perform thorough evaluation to determine the
capacitance of CDLY.
Remark All of the above are approximate calculation formulas at Ta = +25°C.
25