S-77100 Datasheet, PDF (10/40 Pages) Seiko Instruments Inc – POWER SEQUENCER

POWER SEQUENCER
S-77100/77101 Series
Rev.1.0_01
_______
_______
1. 2 S-77101A (Reverse type, with OFF pin), S-77101B (Forward type, with OFF pin)
The _{_}S_{__}-_{_}7_{__}7_{_} 101 Series has enable outputs of 3 channels (the ENBL_A pin, the ENBL_B pin and the ENBL_C pin) and
the OFF pin. The order of the off-sequence operation is different in reverse type and forward type.
1. 2. 1 Sequence operation outline
(1) On-sequence operation
After the ON pin changes from "L" to "H", the external capacitor (CDLY) charge operation is started, and the
discharge operation is performed when CDLY is fully charged. The period during which this is repeated n times
is the delay time (tDLY), and the ENBL_A pin changes to "H". Similarly, each time tDLY elapses, the ENBL_B pin
and the ENBL_C pin change to "H" in turn. The period from when the ON pin changes from "L" to "H" to when
the ENBL_C pin changes to "H" is called "on-sequence period".
(2) Off-sequence operation
_______
After the OFF pin changes from "H" to "L", CDLY charge operation is started, and the discharge operation is
performed when CDLY is fully charged. The period during which this is repeated n times is tDLY, and the
ENBL_C pin, the ENBL_B pin and the ENBL_A pin change to "L" in turn in S-77101A. The ENBL_A_{__}p_{__}i_{_}n_{__}, the
ENBL_B pin and the ENBL_C pin change to "L" in turn in S-77101B. The period from when the OFF pin
changes from "H" to "L" to when the ENBL_A pin in S-77101A or the ENBL_C pin in S-77101B changes to "L" is
called "off-sequence period".
_______
Do not change the ON pin and the OFF pin during on-sequence period and off-sequence period in order to
perform the sequence operation normally.
The number of times of CDLY charge and discharge which determines tDLY can be selected from 2 times / 4 times
/ 8 times / 16 times as the option. CDLY charge operation and the discharge operation to generate the tDLY are
performed by the constant current circuit. Refer to " Relation between Delay Time and External Capacitor"
for the relation of CDLY and tDLY.
In addition, the period from when the ENBL_A pin, the ENBL_B pin and the ENBL_C pin all change to "H" to
when the off-sequence operation starts is called "power-good period", and the period from when the ENBL_A
pin, the ENBL_B pin and the ENBL_C pin all change to "L" to when the on-sequence operation starts is called
"off period". The sequenc_{__}e_{___}o_{__}peration is not affected even if the ON pin changes from "H" to "L" during
power-good period or the OFF pin changes from "L" to "H" during off period.
Refer to Figure 8 for the peripheral circuit connection example.
Timing charts are shown in Figure 9 and Figure 10 for S-77101A and S-77101B, respectively.
5 V AUX _DC-DC
IN
LDO
OUT
3.3
V
0.1 F
ON
OFF
S-77101 Series
VDD
ENBL_A
ENBL_B
IN OUT
EN
DC-DC
LDO
IN OUT
DC-DC
LDO
IN OUT
2.5 V
I/O(1)
1.8 V _I/O(2)
EN
1.5 V
LOGIC
CDLY
ENBL_C
VSS
EN
DC-DC
LDO
System
Remark The ENBL_x pin is CMOS output.
Figure 8 Perip_h__e__r_a_ l Circuit Connection Example
_______
(S-77101A: Reverse Type, with OFF pin, S-77101B: Forward Type, with OFF pin)
Caution 1. The input should be performed after the power supply voltage applied to the S-77101 Series
becomes stable condition.
2. The above connection diagram does not guarantee successful operation. Perform thorough
evaluation using the actual application to set the constant.
10