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S-77100 Datasheet, PDF (7/40 Pages) Seiko Instruments Inc – POWER SEQUENCER | |||
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Rev.1.0_01
POWER SEQUENCER
S-77100/77101 Series
ï® Electrical Characteristics
Table 6
(Ta = â40°C to +85°C, VDD = 2.2 V to 5.5 V, VSS = 0 V unless otherwise specified)
Item
Symbol Applied Pin
Condition
Min. Typ.*1 Max. Unit
Operation power supply voltage VDD
Current consumption 1
(Off period)
IDD1
VDD
VDD
â
VDD = 3.3__V__,___
ON pin, OFF pin*2 = VSS,
ENBL_x pin = Open
2.2
â
5.5
V
â
3.0
6.0 μA
Current consumption 2
(Power-good period)
IDD2
VDD
VDD = 3.3__V__,___
ON pin, OFF pin*2 = VDD,
ENBL_x pin = Open
â
3.0
6.0 μA
Current consumption 3
(On-sequence period,
off-sequence period)
IDD3
VDD
VDD = 3.3__V__,___
ON pin, OFF pin*2 = VDD or VSS,
â
ENBL_x pin = Open
â
8.0 μA
Low voltage detection voltage VUVLO
VDD
_______
â
High level input leakage current IIZH
ON, OFF *2
_______
VIN = VDD
Low level input leakage current IIZL
ON, OFF *2 VIN = VSS
Input voltage
_______
VIL
ON, OFF *2
â
(When Schmitt trigger input
_______
is selected)
VIH
ON, OFF *2
â
Input threshold voltage
_______
(When comparator input
VIT_ON
ON, OFF *2
â
is selected)
1.85
2.0
2.13 V
â0.3
â
0.3 μA
â0.3
â
0.3 μA
VSS â
0.3
â
0.2 Ã
VDD
V
0.8 Ã
VDD
â
VDD +
0.3
V
0.3
0.8
1.3
V
ENBL_A,
High level output leakage
current*3
IOZH
ENBL_B,
ENBL_C,
VOUT = VDD
ENBL_D*4
â0.3
â
0.3 μA
ENBL_A,
Low level output leakage
current*3
IOZL
ENBL_B,
ENBL_C,
VOUT = VSS
ENBL_D*4
â0.3
â
0.3 μA
ENBL_A,
Low level output voltage
VOL
ENBL_B,
ENBL_C,
IOL = 2.0 mA
ENBL_D*4
â
â
0.4
V
ENBL_A,
High level output voltage*5
VOH
ENBL_B,
ENBL_C,
IOH = â0.4 mA
ENBL_D*4
0.8 Ã
VDD
â
â
V
ENBL_A,
Ta = +25°C, VDD = 3.3 V,
The period from ENBL_A pin
Delay time*6
tDLY
ENBL_B,
ENBL_C,
rising to ENBL_B pin rising,
CDLY = 10 nF,
40
45
50 ms
ENBL_D*4 The number of times of CDLY
charge and discharge = 4 times
*1. Typ. values are the values at the time of Ta = +25°C.
*2. The S-77101 Series only
*3. When Nch open-drain output is selected as the option.
*4. The S-77100 Series only
*5. When CMOS output is selected as the option.
*6. The delay time varies depending on the usage environment. Perform thorough evaluation using the actual application to
set the constant. Refer to "ï® Relation between Delay Time and External Capacitors" for details.
7
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