S-7600A Datasheet, PDF (6/60 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
LIST OF TABLES
TABLE 3-1 PIN ASSIGNMENT .................................................................................................................. 3-1
TABLE 3-2 PIN DESCRIPTION.................................................................................................................. 3-3
TABLE 4-1 ABSOLUTE MAXIMUM RATINGS .............................................................................................. 4-1
TABLE 4-2 RECOMMENDED OPERATING CONDITIONS .............................................................................. 4-1
TABLE 4-3 DC CHARACTERISTICS .......................................................................................................... 4-2
TABLE 4-4 POWER CURRENT CONSUMPTION.......................................................................................... 4-2
TABLE 5-1 INTERFACE SELECTION.......................................................................................................... 5-1
TABLE 5-2 CONNECTION RELATIONSHIP BETWEEN MPU AND PINS .......................................................... 5-1
TABLE 5-3 68K FAMILY MPU WRITE CYCLE TIMING................................................................................ 5-2
TABLE 5-4 68K FAMILY MPU READ CYCLE TIMING ................................................................................. 5-3
TABLE 5-5 X80 FAMILY MPU WRITE CYCLE TIMING................................................................................ 5-4
TABLE 5-6 X80 FAMILY MPU READ CYCLE TIMING ................................................................................. 5-5
TABLE 5-7 SERIAL INTERFACE WRITE CYCLE TIMING .............................................................................. 5-6
TABLE 5-8 SERIAL INTERFACE READ CYCLE TIMING................................................................................ 5-7
TABLE 5-9 INTERRUPT SELECTION TABLE ............................................................................................... 5-8
TABLE 6-1 S-7600A MEMORY MAP (BANK 0) ......................................................................................... 6-2
TABLE 6-2 S-7600A MEMORY MAP (BANK 1) ......................................................................................... 6-2
TABLE 7-1 IAPI REGISTER MAP ............................................................................................................. 7-2
TABLE 7-2 IAPI REGISTER MAP (CONTINUED) ........................................................................................ 7-3
TABLE 7-3 REVISION REGISTER BIT DEFINITIONS.................................................................................... 7-4
TABLE 7-4 REVISION REGISTER DESCRIPTION ........................................................................................ 7-4
TABLE 7-5 GENERAL CONTROL REGISTER BIT DEFINITIONS .................................................................... 7-4
TABLE 7-6 GENERAL CONTROL REGISTER DESCRIPTION......................................................................... 7-4
TABLE 7-7 GENERIC SOCKET LOCATION REGISTER BIT DEFINITIONS ....................................................... 7-5
TABLE 7-8 GENERIC SOCKET LOCATION REGISTER DESCRIPTION ........................................................... 7-5
TABLE 7-9 MASTER INTERRUPT REGISTER BIT DEFINITIONS.................................................................... 7-5
TABLE 7-10 MASTER INTERRUPT REGISTER DESCRIPTIONS (CONTINUED) ............................................... 7-6
TABLE 7-11 CONF STATUS REGISTER BIT DEFINITIONS........................................................................... 7-6
TABLE 7-12 CONF STATUS REGISTER DESCRIPTION ............................................................................... 7-7
TABLE 7-13 SERIAL PORT INTERRUPT REGISTER BIT DEFINITIONS .......................................................... 7-8
TABLE 7-14 SERIAL PORT INTERRUPT REGISTER DESCRIPTION............................................................... 7-8
TABLE 7-15 SERIAL PORT INTERRUPT MASK REGISTER BIT DEFINITIONS................................................. 7-8
TABLE 7-16 SERIAL PORT INTERRUPT MASK REGISTER DESCRIPTION ..................................................... 7-8
TABLE 7-17 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X10) .......................................................... 7-9
TABLE 7-18 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X11) .......................................................... 7-9
TABLE 7-19 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X12) ........................................................ 7-10
TABLE 7-20 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X13) ........................................................ 7-10
TABLE 7-21 INDEX REGISTER BIT DEFINITION ....................................................................................... 7-10
TABLE 7-22 INDEX REGISTER DESCRIPTION.......................................................................................... 7-10
TABLE 7-23 SOCKET CONFIG STATUS LOW REGISTER BIT DEFINITIONS ................................................ 7-11
TABLE 7-24 SOCKET CONFIG STATUS LOW REGISTER DESCRIPTION..................................................... 7-12
TABLE 7-25 SOCKET STATUS MID REGISTER BIT DEFINITIONS .............................................................. 7-13
TABLE 7-26 SOCKET STATUS MID REGISTER DESCRIPTION................................................................... 7-13
TABLE 7-27 SOCKET ACTIVATE REGISTER BIT DEFINITIONS .................................................................. 7-14
TABLE 7-28 SOCKET ACTIVATE REGISTER DESCRIPTION....................................................................... 7-14
TABLE 7-29 SOCKET INTERRUPT REGISTER BIT DEFINITIONS ................................................................ 7-14
TABLE 7-30 SOCKET INTERRUPT REGISTER DESCRIPTION .................................................................... 7-15
TABLE 7-31 SOCKET DATA AVAIL REGISTER BIT DEFINITIONS ............................................................... 7-15
TABLE 7-32 SOCKET DATA AVAIL REGISTER DESCRIPTION ................................................................... 7-15
TABLE 7-33 SOCKET INTERRUPT MASK LOW REGISTER BIT DEFINITIONS .............................................. 7-16
TABLE 7-34 SOCKET INTERRUPT MASK LOW REGISTER DESCRIPTION................................................... 7-16
TABLE 7-35 SOCKET INTERRUPT MASK HIGH REGISTER BIT DEFINITIONS.............................................. 7-16
TABLE 7-36 SOCKET INTERRUPT MASK HIGH REGISTER DESCRIPTION .................................................. 7-16
TABLE 7-37 SOCKET INTERRUPT LOW REGISTER BIT DEFINITIONS ........................................................ 7-17
TABLE 7-38 SOCKET INTERRUPT LOW REGISTER DESCRIPTION............................................................. 7-17
TABLE 7-39 SOCKET INTERRUPT HIGH REGISTER BIT DEFINITIONS ....................................................... 7-17
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Seiko Instruments Inc.