S-7600A Datasheet, PDF (34/60 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
Table 7-12
Conf Status Register Description
Bit
Bit Name
7 S_DAV
6 DCD
5 DSR / HWFC
4 CTS
3 RI
2 DTR
1 RTS
0 SCTL
Access
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Description
Serial Port Data Available
When read, bit indicates that Serial Port data is
available.
This bit should be written 0.
Carrier Detect
This bit reflects the current state of the DCD bit on
the serial port. It is independent of the SCTL bit
setting.
This bit should be written 0.
Data Send Ready / Hardware Flow Control
When read, this bit reflects the current state of the
DSR bit on the serial port.
When this bit written:
0 = Hardware Flow control is deactivated
1 = Hardware Flow control activated
Refer to Chapter 8 for more information about
Hardware Flow Control.
Clear To Send
This read-only bit reflects the current state of the
CTS bit on the serial port. It is independent of the
SCTL bit setting.
Ring Indicator
This read-only bit reflects the current state of the RI
bit on the serial port. It is independent of the SCTL
bit setting.
Data Terminal Ready
Reading this bit follows the current state of the
DTR bit on the serial port. The MPU can control the
DTR by writing to this bit.
Request To Send
Reading this bit follows the current state of the
RTS bit on the serial port. The MPU can control the
RTS by writing to this bit.
Serial Port Control
This bit determines who controls the serial port.
When this bit is low (default), the MPU controls the
port. When the SCTL bit is high, the network stack
controls the serial serial port.
0 = MPU controls serial port
1 = Hardware controls serial port
7-7
Seiko Instruments Inc.