S-7600A Datasheet, PDF (44/60 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
7.3.21. Socket Interrupt Low Register (0x2C)
(Read/Write, Default 0x00)
This register reports certain interrupt conditions. When an interrupt condition occurs and its enable bit is
set, the hardware sets the corresponding bit. Writing a "1" to the bit clears it. Disabling the corresponding
enable bit prevents the interrupt from showing.
Table 7-37
Socket Interrupt Low Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
TO Buff_Emplty
Buff_Full
Data_Avail -
-
-
-
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.
Table 7-38
Socket Interrupt Low Register Description
Bit
Bit Name
7 TO
6 Buff_Empty
5 Buff_Full
4 Data_Avail
Access
R/W
R/W
R/W
R/W
Description
This interrupt is generated when a timeout condition
occurred while trying to establish a connection.
Writing a “1” to this bit clears the interrupt.
This interrupt is generated when outgoing buffer is
empty. Writing a “1” to this bit clears the interrupt.
This interrupt is generated when the outgoing buffer is
full (1023 bytes). Writing a “1” to this bit clears the
interrupt. Do not use this bit in UDP.
This interrupt is generated when data is available from
the incoming buffer. Writing a “1” to this bit clears the
interrupt.
7.3.22. Socket Interrupt High Register (0x2D)
(Read/Write, Default 0x00)
This register reports certain interrupt conditions. When an interrupt condition occurs and its enable bit is
set, the hardware sets the corresponding bit. Writing a "1" to the bit clears it. Disabling the corresponding
enable bit prevents the interrupt from showing.
Table 7-39
Socket Interrupt High Register Bit Definitions
Bit
7
6
5
4
3
2
1
0
Def.
URG
RST
Term
ConU
-
-
-
-
Default
0
0
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as “0”.
7-17
Seiko Instruments Inc.