S-7600A Datasheet, PDF (56/60 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
9. Reset Functions
9.1. Overview
The S-7600A has two reset functions which are hardware reset and software reset.
9.1.1. Hardware Reset Function
The S-7600A operates to be synchronous to the CLK signal(clock input). When the RESETX pin set to
low level in two clock period minimum, the S-7600A accept hardware reset input and starts initializing
internal circuit at positive edge timing of forth clock. After the RESETX pin return to high level, the S-
7600A maintains initialized state and turns normal state at positive edge timing of forth clock.
See the Figure 9-1.
RESETX
CLK
Min. 2 clock
1st ^{2nd 3rd 4th 1st}
2nd _3rd
4th
Figure 9-1
initialized
Hardware Reset Timing
normal
9.1.2. Software Reset Function
The S-7600A is able to initialize the internal circuit by the General Control Register(0x01). Show the reset
timing in case of x80 Family MPU mode. See the Figure 9-2.
CS
RS
WRITEX
SD7 to 0
BUSYX
CLK
Address
Data h01
Figure 9-2
normal state initialized state
x80 Family MPU mode
Software Reset Timing
normal state
9-1
Seiko Instruments Inc.