S-7600A Datasheet, PDF (51/60 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
8. Data Communications
8.1. Overview
The S-7600A chip contains a on-board serial port for physical transports. The data format of the serial
port is fixed at 1 start bit (logic "0"), 8 data bits, 1 stop bit (logic "1") and no parity bits. The data bits are
sent out, least significant bit first. This data format is shown in Figure 8-1. Also included with the serial
port is a 16- byte Receive FIFO and 1-byte Send Buffer.
Figure 8-1
Serial Data Format
rxd / txd
start D0 D1 D2 D3 D4 D5 D6 D7 stop
8.2. Serial Port Register Map
The following registers are used to communicate with the serial port.
Table 8-1
Serial Port Register Map
Add
0x08
Register
Serial_Port_Config
S_DAV DCD
Bit Definitions
DSR/ CTS RI DTR RTS
HWFC
0x09 Serial_Port_Int
0x0A Serial_Port_Int_
Mask
0x0B Serial_Port_Data
0x0C - BAUD_Rate_Div
0x0D
PT_INT -
-
PINT_E DSINT_ -
N
EN
-
--
-
-
--
-
Serial Port Data Register
BAUD Rate Divider Registers
SCTL
-
-
Seiko Instruments Inc.
8-1