S-7600A Datasheet, PDF (21/60 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
5.2.2. x80 Family MPU Mode
This mode is selected by pulling the C86 input pin “L” and the PSX input pin “H”. In this mode, the
address and data are muxed onto a single 8-bit bus. All cycles start with the address placed on the bus.
This address is then latched internally on the rising edge of WRITEX. The RS pin “L” indicates that the
WRITEX strobe is for the address phase. In the next phase, data is either written or read by generating
WRITEX or READX strobe. The MPU interface logic will assert the BUSYX signal after READX or
WRITEX strobes are de-asserted. The BUSYX signal is de-asserted after the S-7600A complete a read
or writes operation. The MPU samples the BUSYX signal before starting a new cycle. The MPU can
initiate a new cycle after the BUSYX signal gets de-asserted.
5.2.2.1. Write Cycle Timing
CS
RS
READX
WRITEX
SD7 to 0
BUSYX
CLK
TAW8
TCC8
TAH8
TAW8
TCYC8
TDS8
TDH8
Address
read
TBD8
TCC8
TAH8
TDS8
TDH8
Data
read
TBC8
Figure 5-3
x80 Family MPU Write Cycle Timing
TBOD8
Symbol
Description
Min
Max
Notes
T_CYC8
T_AH8
T_AW8
T_DS8
T_DH8
T_CC8
T_BD8
T_BC8
T_BOD8
System Cycle Time
Address Hold Time
Address Setup Time
Data Setup time
Data Hold Time
Control Pulse Width
BUSYX Delay Time
BUSYX Pulse Width
BUSYX Output Disable Time
100 ns
20ns
20ns
20ns
20 ns
40 ns
-
2CLK
-
-
-
-
-
-
1.9CLK
30ns
-
30ns
CL=80pF
CL=80pF
NOTES: • CLK is the clock of S-7600A
• Timing is specified of 50% of the signal waveform.
• Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-5
x80 Family MPU Write Cycle Timing
Seiko Instruments Inc.
5-4