S-7600A Datasheet, PDF (52/60 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
8.2.1. Hardware Flow Control (RTS/CTS Handshaking)
The Hardware Flow Control is turned off by default. In this mode, data is transmitted independent of the
state of the CTSX signal. While the MPU is in control of the serial port, it can monitor the state of all the
serial port control signals and control when data gets sent or received, either through polling the status
bits or interrupts. It can also control the RTSX signal by asserting the RTS bit in the Serial Port Config
register. When the S-7600A controls the serial port, data will be sent out as soon as it is available from
the PPP layer. When receiving data, the software in the MPU control mode should read the data out of
the 16-byte FIFO fast enough to prevent buffer overflow.
Hardware Flow Control can be turned on by writing a "1" to bit 5 (DSR/HWFC) of the Serial Port Config
Register (0x08). With the hardware flow control turned on, full RTS/CTS handshaking is supported.
When the serial port detects that CTS is de-asserted, it will stop sending data until CTS is reasserted.
Any byte output at the time CTS is de-asserted will complete, but no further bytes will be sent until CTS is
asserted.
In the other direction, the S-7600A will de-assert RTS if the serial port’s 16-byte FIFO is half full. This
indicates to the machine on the other end of the serial line to stop transmitting data. The RTS bit will
reassert when the MPU or the S-7600A has read data out of the Receive FIFO and room becomes
empty. If the machine communicating with the S-7600A over the serial port does not support RTS/CTS
handshaking, the Receive FIFO may overflow and data loss will occur.
8.2.2. Serial Port Control
The control of the serial port is turned over to the MPU by default and after any reset condition. In this
mode, any data written to the Serial Port Data register will be sent out and all data received will be made
available to the MPU via this same register. Prior to using the data register, the MPU should set the
BAUD Rate Div register to the proper setting. An interrupt can be triggered when data is available from
the serial port by asserting the PINT_EN bit. When this bit is asserted, an interrupt will trigger any time
that there is data available to be read from the port. If there is more than one byte in the Receive FIFO,
the interrupt will remain active until all bytes are read. An interrupt can also trigger indicating that the
outgoing data byte has been sent, by asserting the DSINT_EN bit. This interrupt will trigger whenever
there is no more data to be sent.
The MPU turns over control to the S-7600A by asserting the SCTL bit in the Serial Port Config register.
When the S-7600A controls the port, the MPU should not access the Serial Port Data register. The S-
7600A chip will automatically send PPP packets to the serial port and read incoming bytes from the serial
port. The serial port interrupts are not valid when the S-7600A controls the port.
8-2
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