S-7600A Datasheet, PDF (19/60 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
5.2.1. 68k Family MPU Mode
This mode can be selected by pulling the C86 input pin “H” and the PSX input pin “H”. In this mode, the
address and data are muxed into a single 8-bit bus. All cycles start by placing an address on the bus and
setting the RS pin to “L”. In this mode WRITEX signal works as read/write(R/WX) signal and READX is
the enable(E) signal for 68k Family MPU interface. After the address cycle, the MPU generates a read or
writes strobe by setting the READX and WRITEX pins. The S-7600A MPU interface logic assert a
BUSYX signal low during data write and read phases. The MPU samples the BUSYX signal before
starting a new cycle. The can initiate a new cycle if the bit is “H”.
5.2.1.1. Write Cycle Timing
CS
RS
W RITEX
(R/W X)
READX
(E)
SD7 to 0
TAW6
TEW
TAH6
TAW6
TCYC6
TDS6
Address
TDH6
TEW
TAH6
TDS6
Data
TDH6
BUSYX
TBD6
TBC6
TBOD6
CLK
Figure 5-1
68k Family MPU Write Timing
Symbol Description
Min
Max
Notes
T_CYC6
T_AH6
T_AW6
T_DS6
T_DH6
T_EW
T_BD6
T_BC6
T_BOD6
System Cycle Time
Address Hold Time
Address Setup Time
Data Setup time
Data Hold Time
Enable Pulse Width
BUSYX Delay Time
BUSYX Pulse Width
BUSYX Output Disable Time
100 ns
20ns
20ns
20ns
20 ns
40 ns
-
2CLK
-
-
-
-
-
-
1.9CLK
30ns
-
30ns
CL=80pF
CL=80pF
NOTES: • CLK is the clock of S-7600A
• Timing is specified of 50% of the signal waveform.
• Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-3
68k Family MPU Write Cycle Timing
Seiko Instruments Inc.
5-2