S-7600A Datasheet, PDF (24/60 Pages) Seiko Instruments Inc – Hardware Specification (TCP/IP Network Stack LSI)

TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
5.3.2. Read Cycle Timing
CS
RS
W RITEX
(R/W X)
SD6
(SCL)
SD7
(SI)
SD5
(SO)
BUSYX
TASS
TCYCS
TAHS
TCLHS
TASS
TAHS
TCLLS
TDSS
TDHS
A7 A6 A5 A4 A3 A2 A1 A0
TDDS
TOHS
A7 A6 A5 A4 A3 A2 A1 A0
TBDS
TBCS
TASS
TDDS
TAHS
TOHS
D7 D6 D5 D4 D3 D2 D1 D0
TBODS
CLK
Figure 5-6
Serial Interface Read Timing
Symbol Description
Min
Max
Notes
T_CYCS
T_CLLS
T_CLHS
T_ASS
T_AHS
T_DSS
T_DHS
T_DDS
T_OHS
T_BDS
T_BCS
T_BODS
System Cycle Time
Clock L Time
Clocl H Time
Address Setup Time
Address Hold Time
Data Setup time
Data Hold Time
Data delay Time
Output Disable Time
BUSYX Delay Time
BUSYX Pulse Width
BUSYX Output Disable Time
100 ns
40ns
40 ns
20ns
20ns
20ns
20 ns
-
-
-
2CLK
-
1.9CLK
-
-
-
-
-
-
30ns
20ns
30ns
-
30ns
CL=80pF
CL=80pF
CL=80pF
CL=80pF
NOTES: • CLK is the clock of S-7600A
• Timing is specified of 50% of the signal waveform.
• Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-8
Serial Interface Read Cycle Timing
5-7
Seiko Instruments Inc.