SAB80C515A-5 Datasheet, PDF (87/108 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller Family

SAB 80C515A/83C515A-5
Requirements for Hardware Power Down Mode
There is no dedicated pin to enable the Hardware Power Down Mode. The control pin PE/SWD
has no control function in this mode. It enables and disables only the use of software controlled
power saving modes.
Software Controlled Power Saving Modes
All of these modes are entered by software. Special function register PCON (power control
register, address is 87_H) is used to select one of these modes.
Slow Down Mode
During slow down operation all signal frequencies that are derived from the oscillator clock, are
divided by eight, also the clockout signal and and the watchdog timer count.
The slow down mode is enabled by setting bit SD. The controller actually enters the slow down
mode after a short synchronisation period (max. 2 machine cycles).
The slow down mode is disabled by clearing bit SD.
Idle Mode
During idle mode all peripherals of the SAB 80C515A (except for the watchdog timer) are still
supplied by the oscillator clock. Thus the user has to take care which peripheral should
continue to run and which has to be stopped during Idle.
The procedure to enter the Idle mode is similar to the one entering the power down mode. The
two bits IDLE and IDLS must be set by two consecutive instructions to minimize the chance of
unintentional activating of the idle mode.
There are two ways to terminate the idle mode:
– The idle mode can be terminated by activating any enabled interrupt. This interrupt will be
serviced and the instruction to be executed following the RETI instruction will be the one
following the instruction that set the bit IDLS.
– The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still
running, the hardware reset must be held active only for two machine cycles for a complete
reset.
Normally the port pins hold the logical state they had at the time idle mode was activated. If
some pins are programmed to serve their alternate functions they still continue to output during
idle mode if the assigned function is on. The control signals ALE and PSEN hold at logic high
levels (see table 5).
Semiconductor Group
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