SAB80C515A-5 Datasheet, PDF (48/108 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller Family

On-Chip Peripheral Components
Refreshing the Watchdog Timer
At the same time the Watchdog Timer is started, the 7-bit register WDTH is preset by the contents
of WDTREL.0 to WDTREL.6. Once started the Watchdog Timer cannot be stopped by software but
can be refreshed to the reload value only by first setting bit WDT (IEN0.6) and by the next instruction
setting SWDT (IEN1.6). Bit WDT will automatically be cleared during the second machine cycle
after having been set ¹⁾. This double-instruction refresh of the Watchdog Timer is implemented to
minimize the chance of an unintentional reset of the watchdog unit.
The reload register WDTREL can be written at any time, as already mentioned. Therefore, a
periodical refresh of WDTREL can be added to the above mentioned starting procedure of the
Watchdog Timer. Thus a wrong reload value caused by a possible distortion during the write
operation to WDTREL can be corrected by software.
Watchdog Reset and Watchdog Status Flag (WDTS)
If the software fails to clear the watchdog in time, an internally generated watchdog reset is entered
at the counter state 7FFCH. The duration of the reset signal then depends on the prescaler
selection (either 8 or 128 cycles). This internal reset differs from an external one in so far as the
Watchdog Timer is not disabled and bit WDTS is set. Figure 5-6 shows a block diagram of all reset
requests in the SAB 80C515A and the function of the watchdog status flag. The WDTS is a flip-flop,
which is set by a Watchdog Timer reset and can be cleared by an external hardware reset. Bit
WDTS allows the software to examine from which source the reset was activated. The bit WDTS
can also be cleared by software.
1) _{(SETB - Instructions have to be used)}
Semiconductor Group
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