SAB80C515A-5 Datasheet, PDF (40/108 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller Family

On-Chip Peripheral Components
A/D Converter Timing
After a conversion has been started (by a write to ADDATL, external start by P4.0/ADST or in
continuous mode) the analog input voltage is sampled for 4 clock cycles. The analog source must
be capable of charging the capacitor network of appr. 50 pF to full accuracy in this time. During this
period the converter is susceptable to spikes and noise at the analog input, which may cause wrong
codes at the digital outputs. Therefore RC-filtering at the analog inputs is recommended (see figure
below).
Conversion of the sampled analog voltage takes place between the 4th an 14th clock cycle.
Figure 5-3
Recommended RC-Filtering at the Analog Inputs
Semiconductor Group
5-7