SAB80C515A-5 Datasheet, PDF (86/108 Pages) Siemens Semiconductor Group – 8-Bit CMOS Single-Chip Microcontroller Family

SAB 80C515A/83C515A-5
Power Saving Modes
The SAB 80C515A provides – due to Siemens ACMOS technology – four modes in which
power consumption can be significantly reduced.
– The Slow Down Mode
The controller keeps up the full operating functionality, but is driven with one eight of its
normal operating frequency. Slowing down the frequency remarkable reduces power
consumption.
– The Idle Mode
The CPU is gated off from the oscillator, but all peripherals are still supplied with the clock
and continue working.
– The Software Power Down Mode
Operation of the SAB 80C515A is stopped, the on-chip oscillator and the RC-oscillator are
turned off. This mode is used to save the contents of the internal RAM with a very low
standby current and is fully compatible to the Power Down Mode of the SAB 80C515.
– The Hardware Power Down Mode
Operation of the SAB 80C515A is stopped, the on-chip oscillator and the RC-oscillator are
turned off. The pin HWPD controls this mode. Port pins and several control lines enter a
floating state. The Hardware Power Down Mode is new in the SAB 80C515A and is
independent of the state of pin PE/SWD (which enables only the software initiated power
reduction modes).
Hardware Enable for Software controlled Power Saving Modes
A dedicated pin PE/SWD of the SAB 80C515A allows to block the Software controlled power
saving modes. Since this pin is mostly used in noise-critical application it is combined with an
automatic start of the Watchdog Timer.
PE/SWD = V_IH (logic high level):
Using of the power saving modes is not possible. The
watchdog timer starts immediately after reset. The
instruction sequences used for entering of power saving
modes will not affect the normal operation of the device.
PE/SWD = V_IL (logic low level):
All power saving moes can be activated by software. The
watchdog timer can be started by software at any time.
When left unconnected, pin PE/SWD is pulled high by a weak internall pull-up. This is done to
provide system protection on default.
The logic-level applied to pin PE/SWD can be changed during program execution to allow or to
block the use of the power saving modes without any effect on the on-chip watchdog circuitry.
Semiconductor Group
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