SDA9189X Datasheet, PDF (35/55 Pages) Siemens Semiconductor Group – Quarter PIP Processor

SDA 9189X
Detailed Description (cont’d)
Bit
Name
Function
Subaddress 05
D7 … D4 WRPOS
D3 … D2 PMOD
D1 … D0 IMOD
Multi-PIP diplay modes: selection of partial picture for writing
(position number depends on the chosen display mode,
see diagrams).
At single-PIP display modes WRPOS must be set
to ‘0000’.
00: automatic detection of line standard (parent signal)
01: fixed adjustment 625 lines
10: fixed adjustment 525 lines
11: freeze last line standard
00: automatic detection of line standard (inset signal)
01: fixed adjustment 625 lines
10: fixed adjustment 525 lines
11: freeze last line standard
Subaddress 06
D5
BCKCOL
D4 … D0 HSIDEL
0: inset pictures visible (normal mode)
1: PIP picture filled with luminance value of the background
color BCKY (see Subaddress 10 on page 38).
The chrominance components are set to ‘0’.
Delay of the horizontal synchronization pulse of the inset
signal (in steps of 4 periods of 13.5 MHz clock) for the
purpose of shifting the decimated part of a line.
Warning: adjustment of HSIDEL will influence the adjustment
of VSIDEL (subaddr. 07) (see chapter 4.3).
Semiconductor Group
35
03.96