SDA9189X Datasheet, PDF (31/55 Pages) Siemens Semiconductor Group – Quarter PIP Processor

SDA 9189X
2.7 Numerical PLL
A numerical PLL circuit supplies a clock of about 27 MHz with high stability. The nominal
quartz frequency is 20.48 MHz. The generated clock is locked to the parent horizontal
synchronization pulses. Its frequency varies with the frequency of this signal. Four
different characteristics of the PLL behavior can be chosen to handle synchronization
signals from various sources (PLLTC).
If the PLL is switched OFF an external 13.5 or 27 MHz parent line locked clock can be
fed to the IC. Using up to three SDA 9189X ICs in the same application only one quartz
is necessary.
Note: Before setting bit D3 of subaddress 00 (READ27) noise reduction of the VSP
pulse must be switched OFF (D5 of subaddress 08 = ‘1’).
2.8 I²C Bus
2.8.1 I²C Bus Addresses
Three different I²C Bus addresses are programmable via pin ADR.
Pin ADR
Low level (V_SS or V_SSA)
Mid level (open)
High level (V_DD or V_DDA)
Address (BIN)
1101011
1101110
1101111
Address (HEX)
D6
DC
DE
2.8.2 I²C Bus Receiver Format
S Address 0 A Subaddress
A Data Byte A ***
AP
S: Start condition
A: Acknowledge
P: Stop condition
Only write operation is possible. An automatical address increment function is
implemented.
Semiconductor Group
31
03.96